职位描述
* 根据处理器架构与微架构制定验证计划
* 负责处理器验证流程及验证平台的搭建, 调试与维护
* 负责编写测试激励收集覆盖率, 完成处理器验证交付
* Make testplan based on processor architecture and micro-architecture
* Develop verification flow, responsible for the build-up, debugging and maintenance of the verification platform
* Writing test stimulus, coverage closure and complete verification sign-off
职位要求
* 熟悉ASIC设计验证开发流程, 精通UVM验证方法学
* 熟悉Verilog, SystemVerilog及各种EDA工具
* 熟悉Perl, Python, Shell等脚本语言
* 良好的沟通能力, 良好的解决问题的能力, 具备团队合作精神
* 熟悉RISC-V, ARM, MIPS等处理器架构与微架构为加分项
* 熟悉处理器仿真器或随机指令发生器为加分项
* 熟悉C/C++/汇编等编程语言为加分项
* Familiar with the ASIC verification development flow. Good at UVM methodology
* Familiar with Verilog, SystemVerilog and EDA tools
* Familiar with scripts such as Perl, Python, Shell etc
* Good communication skills and ability to fix issues. Good team worker
* Familiar with one of the processor architectures such as RISC-V, ARM, MIPS etc is a big plus
* Familiar with processor simulator or random instruction generator is a big plus
* Familiar with C/C++/Assembly language is a big plus
base:北京 北京市朝阳区启阳路金辉大厦